D9.30 TRCIDR1, ID Register 1
The TRCIDR1 returns the base architecture of the trace unit.
Bit field descriptions
The TRCIDR1 is a 32-bit register.
31 0
TRCARCHMAJ
24 23 16 15 12 11 8 7 4 3
DESIGNER REVISION
TRCARCHMIN
RES0
RES1
Figure D9-28 TRCIDR1 bit assignments
DESIGNER, [31:24]
Indicates which company designed the trace unit:
0x41 Arm.
RES0, [23:16]
RES0 Reserved.
RES1, [15:12]
RES1 Reserved.
TRCARCHMAJ, [11:8]
Major trace unit architecture version number:
0b0100 ETMv4.
TRCARCHMIN, [7:4]
Minor trace unit architecture version number:
0x2 ETMv4.2
REVISION, [3:0]
Trace unit implementation revision number:
3 ETM revision.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIDR1 can be accessed through the external debug interface, offset 0x1E4.
D9 ETM registers
D9.30 TRCIDR1, ID Register 1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-536
Non-Confidential
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