Return stack support:
1 Return stack implemented.
RES0, [8]
RES0 Reserved.
TRCCCI, [7]
Support for cycle counting in the instruction trace:
1 Cycle counting in the instruction trace is implemented.
TRCCOND, [6]
Support for conditional instruction tracing:
0 Conditional instruction tracing is not supported.
TRCBB, [5]
Support for branch broadcast tracing:
1 Branch broadcast tracing is implemented.
TRCDATA, [4:3]
Conditional tracing field:
0b00 Tracing of data addresses and data values is not implemented.
INSTP0, [2:1]
P0 tracing support field:
0b00 Tracing of load and store instructions as P0 elements is not supported.
RES1, [0]
RES1 Reserved.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIDR0 can be accessed through the external debug interface, offset 0x1E0.
D9 ETM registers
D9.29 TRCIDR0, ID Register 0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-535
Non-Confidential
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