ARM Cortex-A76 Core User Manual

D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
The TRCSSCCR0 controls the single-shot comparator.
Bit field descriptions
The TRCSSCSR0 is a 32-bit register
31 20 19 16 15 8 7 0
ARC SAC
24 2325
RST
RES0
Figure D9-62 TRCSSCCR0 bit assignments
RES0, [31:25]
RES0 Reserved.
RST, [24]
Enables the single-shot comparator resource to be reset when it occurs, to enable another
comparator match to be detected:
1 Reset enabled. Multiple matches can occur.
RES0, [23:20]
RES0 Reserved.
ARC, [19:16]
Selects one or more address range comparators for single-shot control.
One bit is provided for each implemented address range comparator.
RES0, [15:8]
RES0 Reserved.
SAC, [7:0]
Selects one or more single address comparators for single-shot control.
One bit is provided for each implemented single address comparator.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSSCCR0 can be accessed through the external debug interface, offset 0x280.
D9 ETM registers
D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
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D9-576
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core