D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
The TRCSSCCR0 controls the single-shot comparator.
Bit field descriptions
The TRCSSCSR0 is a 32-bit register
31 20 19 16 15 8 7 0
ARC SAC
24 2325
RST
RES0
Figure D9-62 TRCSSCCR0 bit assignments
RES0, [31:25]
RES0 Reserved.
RST, [24]
Enables the single-shot comparator resource to be reset when it occurs, to enable another
comparator match to be detected:
1 Reset enabled. Multiple matches can occur.
RES0, [23:20]
RES0 Reserved.
ARC, [19:16]
Selects one or more address range comparators for single-shot control.
One bit is provided for each implemented address range comparator.
RES0, [15:8]
RES0 Reserved.
SAC, [7:0]
Selects one or more single address comparators for single-shot control.
One bit is provided for each implemented single address comparator.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSSCCR0 can be accessed through the external debug interface, offset 0x280.
D9 ETM registers
D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-576
Non-Confidential
To Next Page
Loading...
