ARM Cortex-A76 Core User Manual

D9.21 TRCDEVAFF0, Device Affinity Register 0
The TRCDEVAFF0 provides an additional core identification mechanism for scheduling purposes in a
cluster. TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.
Bit field descriptions
The TRCDEVAFF0 is a 32-bit register.
31 30 29 8 7 0
U Aff2 Aff0
25 24
MT
23
Aff1
16 15
RES0
RES1
Figure D9-20 TRCDEVAFF0 bit assignments
RES1, [31]
RES1 Reserved.
U, [30]
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
0 Core is part of a multiprocessor system. This is the value for implementations with
more than one core, and for implementations with an ACE or CHI master interface.
1 Core is part of a uniprocessor system. This is the value for single core
implementations with an AXI master interface.
RES0, [29:25]
RES0 Reserved.
MT, [24]
Indicates whether the lowest level of affinity consists of logical cores that are implemented
using a multithreading type approach. This value is:
0 Performance of cores at the lowest affinity level is largely independent.
Aff2, [23:16]
Affinity level 2. Second highest level affinity field.
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
Aff1, [15:8]
Affinity level 1. Third highest level affinity field.
Indicates the value read in the CLUSTERIDAFF1 configuration signal.
Aff0, [7:0]
Affinity level 0. Lowest level affinity field.
Indicates the core number in the Cortex-A76 core. The possible values are:
0x0 A cluster with one core only.
0x0, 0x1 A cluster with two cores.
0x0, 0x1, 0x2 A cluster with three cores.
D9 ETM registers
D9.21 TRCDEVAFF0, Device Affinity Register 0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-524
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core