ARM Cortex-A76 Core

D9.32 TRCIDR3, ID Register 3
The TRCIDR3 indicates:
• Whether TRCVICTLR is supported.
• The number of cores available for tracing.
• If an exception level supports instruction tracing.
• The minimum threshold value for instruction trace cycle counting.
• Whether the synchronization period is fixed.
• Whether TRCSTALLCTLR is supported and if so whether it supports trace overflow prevention and
supports stall control of the core.
Bit field descriptions
The TRCIDR3 is a 32-bit register.
31 025 24 16 15 1112 5 4
CCITMIN
30 28 20 192327 26
EXLEVEL_S
EXLEVEL_NS
NOOVERFLOW
NUMPROC
SYSSTALL
STALLCTL
SYNCPR
TRCERR
RES0
Figure D9-30 TRCIDR3 bit assignments
NOOVERFLOW, [31]
Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:
0 TRCSTALLCTLR.NOOVERFLOW is not implemented.
NUMPROC, [30:28]
Indicates the number of cores available for tracing:
0b000 The trace unit can trace one core, ETM trace unit sharing not supported.
SYSSTALL, [27]
Indicates whether stall control is implemented:
1 The system supports core stall control.
STALLCTL, [26]
Indicates whether TRCSTALLCTLR is implemented:
1 TRCSTALLCTLR is implemented.
This field is used in conjunction with SYSSTALL.
SYNCPR, [25]
Indicates whether there is a fixed synchronization period:
D9 ETM registers
D9.32 TRCIDR3, ID Register 3
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D9-539
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