ARM Cortex-A76 Core User Manual

B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1
The ID_DFR0_EL1 provides top-level information about the debug system in AArch32.
Bit field descriptions
ID_DFR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 12 11 8 7 04 324 23 20 19 16 1528 27
PerfMon MProfDbg MMapTrc CopTrc CopSDbg CopDbg
RES0
Figure B2-48 ID_DFR0_EL1 bit assignments
RES0, [31:28]
RES0 Reserved.
PerfMon, [27:24]
Indicates support for performance monitor model:
4 Support for Performance Monitor Unit version 3 (PMUv3) system registers, with a
16-bit evtCount field.
MProfDbg, [23:20]
Indicates support for memory-mapped debug model for M profile cores:
0 This product does not support M profile Debug architecture.
MMapTrc, [19:16]
Indicates support for memory-mapped trace model:
1 Support for Arm trace architecture, with memory-mapped access.
In the Trace registers, the ETMIDR gives more information about the implementation.
CopTrc, [15:12]
Indicates support for coprocessor-based trace model:
0 This product does not support Arm trace architecture.
RES0, [11:8]
RES0 Reserved.
CopSDbg, [7:4]
Indicates support for coprocessor-based Secure debug model:
8 This product supports the Armv8.2 Debug architecture.
CopDbg, [3:0]
Indicates support for coprocessor-based debug model:
8 This product supports the Armv8.2 Debug architecture.
B2 AArch64 system registers
B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1
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B2-231
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core