ARM Cortex-A76 Core User Manual

B3.3 ERR0CTLR, Error Record Control Register
The ERR0CTLR contains enable bits for the node that writes to this record:
• Enabling error detection and correction.
• Enabling an error recovery interrupt.
• Enabling a fault handling interrupt.
• Enabling error recovery reporting as a read or write error response.
Bit field descriptions
ERR0CTLR is a 64-bit register and is part of the Reliability, Availability, Serviceability (RAS) registers
functional group.
ERR0CTLR resets to CFI [8], FI [3], and UI [2] are UNKNOWN. The rest of the register is RES0.
63 9 8 7 4 3 2 1 0
CFI
FI
UI
ED
RES0
Figure B3-2 ERR0CTLR bit assignments
RES0, [63:9]
RES0 Reserved.
CFI, [8]
Fault handling interrupt for corrected errors enable.
The fault handling interrupt is generated when one of the standard CE counters on ERR0MISC0
overflows and the overflow bit is set. The possible values are:
0 Fault handling interrupt not generated for corrected errors.
1 Fault handling interrupt generated for corrected errors.
The interrupt is generated even if the error status is overwritten because the error record already
records a higher priority error.
Note
This applies to both reads and writes.
RES0, [7:4]
RES0 Reserved.
FI, [3]
Fault handling interrupt enable.
The fault handling interrupt is generated for all detected Deferred errors and Uncorrected errors.
The possible values are:
0 Fault handling interrupt disabled.
1 Fault handling interrupt enabled.
UI, [2]
B3 Error system registers
B3.3 ERR0CTLR, Error Record Control Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core