ARM Cortex-A76 Core

D9.64 TRCSEQSTR, Sequencer State Register
The TRCSEQSTR holds the value of the current state of the sequencer.
Bit field descriptions
The TRCSEQSTR is a 32-bit register
31 1 0
2
STATE
RES0
Figure D9-61 TRCSEQSTR bit assignments
RES0, [31:2]
RES0 Reserved.
STATE, [1:0]
Current sequencer state:
0b00 State 0.
0b01 State 1.
0b10 State 2.
0b11 State 3.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSEQSTR can be accessed through the external debug interface, offset 0x11C.
D9 ETM registers
D9.64 TRCSEQSTR, Sequencer State Register
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D9-575
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