ARM Cortex-A76 Core User Manual

B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2
The VTCR_EL2 controls the translation table walks required for the stage 2 translation of memory
accesses from Non-secure EL0 and EL1.
It also holds cacheability and shareability information for the accesses.
Bit field descriptions
VTCR_EL2 is a 32-bit register, and is part of:
• The Virtualization registers functional group.
• The Virtual memory control registers functional group.
31 30 29 28 27 26 25 24 23 22 21 20 19
PS
18 16
TG0
15 14
SH0
13 12 11 10 9 8
SL0
7 6
T0SZ
5 0
HWU62
HWU61
HWU60
HWU59
HD
HA
VS
ORGN0
IRGN0
RES1
RES0
Figure B2-86 VTCR_EL2 bit assignments
Note
Bits[28:25] and bits[22:21], architecturally defined, are implemented in the core.
TG0, [15:14]
TTBR0_EL2 granule size. The possible values are:
00 4KB.
01 64KB.
10 16KB.
11 Reserved.
All other values are not supported.
Configurations
RW fields in this register reset to architecturally UNKNOWN values.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-288
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core