ARM Cortex-A76 Core

D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
The TRCCNTRLDVRn define the reload value for the counter.
Bit field descriptions
The TRCCNTRLDVRn is a 32-bit register.
31 16 15 0
VALUE
RES0
Figure D9-17 TRCCNTRLDVRn bit assignments
RES0, [31:16]
RES0 Reserved.
VALUE, [15:0]
Defines the reload value for the counter. This value is loaded into the counter each time the
reload event occurs.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCCNTRLDVRn registers can be accessed through the external debug interface, offsets:
TRCCNTRLDVR0
0x140.
TRCCNTRLDVR1
0x144.
D9 ETM registers
D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
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D9-519
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