ARM Cortex-A76 Core User Manual

D9.72 TRCVICTLR, ViewInst Main Control Register
The TRCVICTLR controls instruction trace filtering.
Bit field descriptions
The TRCVICTLR is a 32-bit register.
31 0789101115 121619202324
SSSTATUS
TRCRESET
TRCERR
EXLEVEL_S
EXLEVEL_NS
6 34
SEL
TYPE
RES0
Figure D9-69 TRCVICTLR bit assignments
RES0, [31:24]
RES0 Reserved.
EXLEVEL_NS, [23:20]
In Non-secure state, each bit controls whether instruction tracing is enabled for the
corresponding exception level:
0 Trace unit generates instruction trace, in Non-secure state, for exception level n.
1 Trace unit does not generate instruction trace, in Non-secure state, for exception level
n.
The exception levels are:
Bit[20] Exception level 0.
Bit[21] Exception level 1.
Bit[22] Exception level 2.
Bit[23] RAZ/WI. Instruction tracing is not implemented for exception level 3.
EXLEVEL_S, [19:16]
In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
exception level:
0 Trace unit generates instruction trace, in Secure state, for exception level n.
1 Trace unit does not generate instruction trace, in Secure state, for exception level n.
The exception levels are:
Bit[16] Exception level 0.
Bit[17] Exception level 1.
Bit[18] RAZ/WI. Instruction tracing is not implemented for exception level 2.
Bit[19] Exception level 3.
RES0, [15:12]
RES0 Reserved.
TRCERR, [11]
D9 ETM registers
D9.72 TRCVICTLR, ViewInst Main Control Register
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D9-583
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core