ARM Cortex-A76 Core User Manual

A7.1 About the L2 memory system
The L2 memory subsystem consist of:
• An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. Cache lines
have a fixed length of 64 bytes.
• Optional ECC protection for all RAM structures except victim array.
• Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
• Configurable CHI interface to the DSU or CHI compliant system with support for 128-bit and 256-bit
data widths.
• Dynamic biased replacement policy.
• Modified Exclusive Shared Invalid (MESI) coherency.
A7 Level 2 memory system
A7.1 About the L2 memory system
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A7-98
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core