ARM Cortex-A76 Core

A7.1 About the L2 memory system
The L2 memory subsystem consist of:
• An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. Cache lines
have a fixed length of 64 bytes.
• Optional ECC protection for all RAM structures except victim array.
• Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache.
• Configurable CHI interface to the DSU or CHI compliant system with support for 128-bit and 256-bit
data widths.
• Dynamic biased replacement policy.
• Modified Exclusive Shared Invalid (MESI) coherency.
A7 Level 2 memory system
A7.1 About the L2 memory system
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