ARM Cortex-A76 Core User Manual

D9.5 TRCAUXCTLR, Auxiliary Control Register
The TRCAUXCTLR provides IMPLEMENTATION DEFINED configuration and control options.
Bit field descriptions
31 08 7
CIFOVERRIDE
FLUSHOVERRIDE
TSIOVERRIDE
6 5 4 3 2 1
SYNCOVERRIDE
FRSYNCOVFLOW
IDLEACKOVERRIDE
AFREADYOVERRIDE
RES0
INOVFLOWEN
Figure D9-4 TRCAUXCTLR bit assignments
RES0, [31:8]
RES0 Reserved.
CIFOVERRIDE, [7]
Override core interface register repeater clock enable. The possible values are:
0 Core interface clock gate is enabled.
1 Core interface clock gate is disabled.
INOVFLOWEN, [6]
Allow overflows of the core interface buffer, removing any rare impact that the trace unit might
have on the core's speculation when enabled. The possible values are:
0 Core interface buffer overflows are disabled.
1 Core interface buffer overflows are enabled.
When this bit is set to 1, the trace start/stop logic might deviate from architecturally-specified
behavior.
FLUSHOVERRIDE, [5]
Override ETM flush behavior. The possible values are:
0 ETM trace unit FIFO is flushed and ETM trace unit enters idle state when DBGEN or
NIDEN is LOW.
1 ETM trace unit FIFO is not flushed and ETM trace unit does not enter idle state when
DBGEN or NIDEN is LOW.
When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.
TSIOVERRIDE, [4]
Override TS packet insertion behavior. The possible values are:
0 Timestamp packets are inserted into FIFO only when trace activity is LOW.
1 Timestamp packets are inserted into FIFO irrespective of trace activity.
SYNCOVERRIDE, [3]
D9 ETM registers
D9.5 TRCAUXCTLR, Auxiliary Control Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core