Override SYNC packet insertion behavior. The possible values are:
0 SYNC packets are inserted into FIFO only when trace activity is low.
1 SYNC packets are inserted into FIFO irrespective of trace activity.
FRSYNCOVFLOW, [2]
Force overflows to output synchronization packets. The possible values are:
0 No FIFO overflow when SYNC packets are delayed.
1 Forces FIFO overflow when SYNC packets are delayed.
When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.
IDLEACKOVERRIDE, [1]
Force ETM idle acknowledge. The possible values are:
0 ETM trace unit idle acknowledge is asserted only when the ETM trace unit is in idle
state.
1 ETM trace unit idle acknowledge is asserted irrespective of the ETM trace unit idle
state.
When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.
AFREADYOVERRIDE, [0]
Force assertion of AFREADYM output. The possible values are:
0 ETM trace unit AFREADYM output is asserted only when the ETM trace unit is in
idle state or when all the trace bytes in FIFO before a flush request are output.
1 ETM trace unit AFREADYM output is always asserted HIGH.
When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.
The TRCAUXCTLR can be accessed through the internal memory-mapped interface and the external
debug interface, offset 0x018.
Configurations
Available in all configurations.
D9 ETM registers
D9.5 TRCAUXCTLR, Auxiliary Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-504
Non-Confidential
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