ARM Cortex-A76 Core User Manual

B3.1 Error system register summary
This section identifies the ERR0* core error record registers accessed by the AArch64 ERX* error
registers.
The ERR0* registers are agnostic to the architectural state. For example, this means that for
ERRSELR==0 and ERRSELR_EL1==0, ERXPFGFR and ERXPFGFR_EL1 will both access
ERR0PFGFR.
For those registers not described in this chapter, see the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile.
The following table describes the architectural error record registers.
Table B3-1 Architectural error system register summary
Register
mnemonic
Size Register name Access aliases from AArch64
ERR0ADDR 64 B3.2 ERR0ADDR, Error Record Address
Register on page B3-293
B2.38 ERXADDR_EL1, Selected Error Record Address
Register, EL1 on page B2-198
ERR0CTLR 64 B3.3 ERR0CTLR, Error Record Control
Register on page B3-294
B2.39 ERXCTLR_EL1, Selected Error Record Control
Register, EL1 on page B2-199
ERR0FR 64 B3.4 ERR0FR, Error Record Feature Register
on page B3-296
B2.40 ERXFR_EL1, Selected Error Record Feature
Register, EL1 on page B2-200
ERR0MISC0 64 B3.5 ERR0MISC0, Error Record
Miscellaneous Register 0 on page B3-298
B2.41 ERXMISC0_EL1, Selected Error Record
Miscellaneous Register 0, EL1 on page B2-201
ERR0MISC1 64 B3.6 ERR0MISC1, Error Record
Miscellaneous Register 1 on page B3-301
B2.42 ERXMISC1_EL1, Selected Error Record
Miscellaneous Register 1, EL1 on page B2-202
ERR0STATUS 32 B3.10 ERR0STATUS, Error Record Primary
Status Register on page B3-307
B2.46 ERXSTATUS_EL1, Selected Error Record Primary
Status Register, EL1 on page B2-207
The following table describes the error record registers that are IMPLEMENTATION DEFINED.
Register
mnemonic
Size Register name Access aliases from AArch64
ERR0PFGCDNR 32 B3.7 ERR0PFGCDNR, Error Pseudo Fault
Generation Count Down Register
on page B3-302
B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo
Fault Generation Count Down Register, EL1
on page B2-203
ERR0PFGCTLR 32 B3.8 ERR0PFGCTLR, Error Pseudo Fault
Generation Control Register on page B3-303
B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo
Fault Generation Control Register, EL1
on page B2-204
ERR0PFGFR 32 B3.9 ERR0PFGFR, Error Pseudo Fault
Generation Feature Register on page B3-305
B2.45 ERXPFGFR_EL1, Selected Pseudo Fault
Generation Feature Register, EL1 on page B2-206
B3 Error system registers
B3.1 Error system register summary
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core