ARM Cortex-A76 Core User Manual

B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1
The ID_PFR2_EL1 provides information about the programmers model and architecture extensions
supported by the core.
Bit field descriptions
ID_PFR2_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 04 3
CSV3
RES0
7
SSBS
Figure B2-63 ID_PFR2_EL1 bit assignments
RES0, [31:8]
RES0 Reserved.
SSBS, [7:4]
1 AArch32 provides the PSTATE.SSBS mechanism to mark regions that are Speculative
Store Bypassing Safe (SSBS).
CSV3, [3:0]
1 Data loaded under speculation with a permission or domain fault cannot be used to
form an address or generate condition codes to be used by instructions newer than the
load in the speculative sequence. This is the reset value.
Configurations
There are no configuration notes.
B2 AArch64 system registers
B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1
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B2-260
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core