ARM Cortex-A76 Core User Manual

C1.3 Debug events
A debug event can be a software debug event or a halting debug event.
A core responds to a debug event in one of the following ways:
• Ignores the debug event.
• Takes a debug exception.
• Enters debug state.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information about the debug events.
C1.3.1 Watchpoint debug events
In the Cortex-A76 core, watchpoint debug events are always synchronous.
Memory hint instructions and cache clean operations, except DC ZVA and DC IVAC, do not generate
watchpoint debug events. Store exclusive instructions generate a watchpoint debug event even when the
check for the control of exclusive monitor fails. Atomic CAS instructions generate a watchpoint debug
event even when the compare operation fails.
C1.3.2 Debug OS Lock
Debug OS Lock is set by the powerup reset, nCPUPORESET.
For normal behavior of debug events and debug register accesses, Debug OS Lock must be cleared. For
more information, see the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
Related references
C1.4 External debug interface on page C1-370
A3.1 About clocks, resets, and input synchronization on page A3-42
C1 Debug
C1.3 Debug events
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core