To Next Page

To Previous Page

C1.2.4 External access permissions to debug registers

External access permission to the debug registers is subject to the conditions at the time of the access.

The following table describes the core response to accesses through the external debug interface.

Table C1-1 External access conditions to registers

Name Condition Description

Off EDPRSR.PU is 0

Core power domain is completely off, or in a low-power state where the

core power domain registers cannot be accessed.

If debug power is off, then all external debug and memory-mapped register

accesses return an error.

DLK

DoubleLockStatus() == TRUE

(EDPRSR.DLK is 1)

OS Double Lock is locked.

OSLK OSLSR_EL1.OSLK is 1 OS Lock is locked.

EDAD

AllowExternalDebugAccess() ==FALSE

External debug access is disabled. When an error is returned because of an

EDAD condition code, and this is the highest priority error condition,

EDPRSR.SDAD is set to 1. Otherwise SDAD is unchanged.

Default - None of the conditions apply, normal access.

The following table shows an example of external register access condition codes for access to a

performance monitor register. To determine the access permission for the register, scan the columns from

left to right. Stop at the first column a condition is true, the entry gives the access permission of the

Table C1-2 External register condition code example

Off DLK OSLK EDAD Default

- - - - RO

C1 Debug

C1.2 Debug register interfaces

reserved.

C1-368

Non-Confidential

Questions and Answers:

Need help?

Do you have a question about the ARM Cortex-A76 Core and is the answer not in the manual?

ARM Cortex-A76 Core Specifications

General