ARM Cortex-A76 Core User Manual

A5.6 Specific behaviors on aborts and memory attributes
This section describes specific behaviors caused by aborts and also describes memory attributes.
MMU responses
When one of the following translation is completed, the MMU generates a response to the requester:
• A L1 TLB hit.
• A L2 TLB hit.
• A translation table walk.
The response from the MMU contains the following information:
• The PA corresponding to the translation.
• A set of permissions.
• Secure or Non-secure.
• All the information required to report aborts. See the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile for more details.
A5.6.1 External aborts
External aborts are defined as those that occur in the memory system rather than those that the MMU
detects. Normally, external memory aborts are rare. External aborts are caused by errors flagged to the
external interface.
When an external abort to the external interface occurs on an access for a translation table walk access,
the MMU returns a synchronous external abort. For a load multiple or store multiple operation, the
address captured in the fault address register is that of the address that generated the synchronous
external abort.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
A5.6.2 Mis-programming contiguous hints
In the case of a mis-programming contiguous hint, when there is a descriptor that contains a set CH bit,
all contiguous VAs contained in this block should be included in the input VA address space that is
defined for stage 1 by TxSZ for TTBx or for stage 2 by {SL0, T0SZ}.
The Cortex-A76 core treats such a block as not causing a translation fault.
A5.6.3 Memory attributes
The memory region attributes specified in the TLB entry, or in the descriptor in case of translation table
walk, determine if the access is:
• Normal Memory or Device type.
• One of the four different device memory types that are defined for Armv8:
Device-nGnRnE Device non-Gathering, non-Reordering, No Early Write Acknowledgment.
Device-nGnRE Device non-Gathering, non-Reordering, Early Write Acknowledgment.
Device-nGRE Device non-Gathering, Reordering, Early Write Acknowledgment.
Device-GRE Device Gathering, Reordering, Early Write Acknowledgment.
In the Cortex-A76 core, a page is cacheable only if the inner memory attribute and outer memory
attribute are Write Back. In all other cases, all pages are downgraded to Non-cacheable Normal memory.
When the MMU is disabled at stage 1 and stage 2, and SCTLR.I is set to 1, instruction prefetches are
cached in the instruction cache but not in the unified cache. In all other cases, normal behavior on
memory attribute applies.
A5 Memory Management Unit
A5.6 Specific behaviors on aborts and memory attributes
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core