ARM Cortex-A76 Core User Manual

B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1
Provides top-level information about the debug system in AArch64.
Bit field descriptions
ID_AA64DFR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
4 38 712 1116 1520 1924 2328 27
063
DebugVerTraceVerPMUVerBRPsWRPsCTX_CMPs
32 31
RES0
Figure B2-39 ID_AA64DFR0_EL1 bit assignments
RES0, [63:32]
RES0 Reserved.
CTX_CMPs, [31:28]
Number of breakpoints that are context-aware, minus 1. These are the highest numbered
breakpoints:
0x1 Two breakpoints are context-aware.
RES0, [27:24]
RES0 Reserved.
WRPs, [23:20]
The number of watchpoints minus 1:
0x3 Four watchpoints.
RES0, [19:16]
RES0 Reserved.
BRPs, [15:12]
The number of breakpoints minus 1:
0x5 Six breakpoints.
PMUVer, [11:8]
Performance Monitors Extension version.
0x4 Performance monitor system registers implemented, PMUv3.
TraceVer, [7:4]
Trace extension:
0x0 Trace system registers not implemented.
DebugVer, [3:0]
Debug architecture version:
0x8 Armv8-A debug architecture implemented.
B2 AArch64 system registers
B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1
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B2-216
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core