ARM Cortex-A76 Core User Manual

A7.2 About the L2 cache
The integrated L2 cache is the Point of Unification for the Cortex-A76 core. It handles both instruction
and data requests from the instruction side and data side of each core respectively.
When fetched from the system, instructions are allocated to the L2 cache and can be invalidated during
maintenance operations.
The L2 cache is invalidated automatically at reset unless the DISCACHEINVLD signal is set HIGH
when the Cortex-A76 core is reset. This signal must be used only in diagnostic mode. If caches are not
invalidated on reset, their functionality cannot be guaranteed. See the Arm
®
DynamIQ
™
Shared Unit
Technical Reference Manual for more information on the DISCACHEINVLD signal.
A7 Level 2 memory system
A7.2 About the L2 cache
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core