ARM Cortex-A76 Core User Manual

B2.33 CTR_EL0, Cache Type Register, EL0
The CTR_EL0 provides information about the architecture of the caches.
Bit field descriptions
CTR_EL0 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
IminLine
31 30 28 27 24 23 20 19 16 15 14 13 4 3 0
CWG ERG DminLine L1Ip
RES0
RES1
29
IDC
Figure B2-29 CTR_EL0 bit assignments
RES1, [31]
RES1 Reserved.
RES0, [30:29]
RES0 Reserved.
IDC, [28]
Data cache clean requirements for instruction to data coherence:
0 Data cache clean to the point of unification is required for instruction to data
coherence, unless CLIDR_EL1.LoC == 0b000 or (CLIDR_EL1.LoUIS == 0b000 &&
CLIDR_EL1.LoUU == 0b000). .
1 Data cache clean to the point of unification is not required for instruction to data
coherence.
IDC reflects the inverse value of the BROADCASTCACHEMAINTPOU pin.
CWG, [27:24]
Cache write-back granule. Log
2
of the number of words of the maximum size of memory that
can be overwritten as a result of the eviction of a cache entry that has had a memory location in
it modified:
0100 Cache write-back granule size is 16 words.
ERG, [23:20]
Exclusives Reservation Granule. Log
2
of the number of words of the maximum size of the
reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive
instructions:
0100 Exclusive reservation granule size is 16 words.
DminLine, [19:16]
Log
2
of the number of words in the smallest cache line of all the data and unified caches that the
core controls:
0100 Smallest data cache line size is 16 words.
B2 AArch64 system registers
B2.33 CTR_EL0, Cache Type Register, EL0
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B2-191
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core