ARM Cortex-A76 Core User Manual

A8.3 Uncorrected errors and data poisoning
When an error is detected, the correction mechanism is triggered. However, if the error is a 2-bit error in
a RAM protected by ECC, then the error is not correctable.
The behavior on an uncorrected error depends on the type of RAM.
Uncorrected error detected in a data RAM
When an uncorrected error is detected in a data RAM, the chunk of data with the error is marked as
poisoned. This poison information is then transferred with the data and stored in the cache if the data is
allocated into another cache. The poisoned information is stored per 64 bits of data, except in the L1 data
cache where it is stored per 32 bits of data.
Uncorrected error detected in a tag RAM
When an uncorrected error is detected in a tag RAM, either the address or coherency state of the line is
not known, and the corresponding data cannot be poisoned. In this case, the line is invalidated and an
error recovery interrupt is generated to notify software that data has potentially been lost.
A8 Reliability, Availability, and Serviceability (RAS)
A8.3 Uncorrected errors and data poisoning
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A8-105
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core