ARM Cortex-A76 Core User Manual

Table A8-1 Cache protection behavior (continued)
RAM Protection type Protection granule Correction behavior
L1 data cache data SECDED 32 bits of data +1 poison bit + 7 bits
for ECC attached to the word.
The cache line that contains the error gets
evicted, corrected in line, and refilled to the
core.
L1 Prefetch History Table
(PHT)
None - -
MMU translation cache 2 interleaved parity
bits
67 bits Entry invalidated, new pagewalk started to
refetch it.
MMU replacement policy None -
MMU biased replacement None -
L2 cache tag
SECDED 128KB L2 - 7 ECC bits for 38 tag
bits
256KB L2 - 7 ECC bits for 37 tag
bits
512KB L2 - 7 ECC bits for 36 tag
bits
Tag is corrected inline.
L2 cache data
SECDED
8 ECC bits for 64 data bits Data is corrected inline.
L2 victim None - -
L2 TQ data SECDED 8 ECC bits for 64 data bits Data is corrected inline.
To ensure that progress is guaranteed even in case of hard error, the core returns corrected data to the
core, and no cache access is required after data correction.
A8 Reliability, Availability, and Serviceability (RAS)
A8.2 Cache protection behavior
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A8-104
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core