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B1.1 AArch32 architectural system register summary

This chapter identifies the AArch32 architectural system registers implemented in the Cortex-A76 core.

The following table identifies the architecturally defined registers that are implemented in the

Cortex-A76 core. For a description of these registers see the Arm

Architecture Reference Manual

Armv8, for Armv8-A architecture profile.

For the registers listed in the following table, coproc==0b1111.

Table B1-1 Architecturally defined registers

Name CRn Opc1 CRm Opc2 Width description

CNTFRQ c14 0 c0 0 32 Timer Clock Ticks per Second

CNTP_CTL c14 0 c2 1 32 Counter-timer Physical Timer Control register

CNTP_CVAL - 2 c14 - 64 Counter-timer Physical Timer CompareValue register

CNTP_TVAL c14 0 c2 0 32 Counter-timer Physical Timer TimerValue register

CNTPCT - 0 c14 - 64 Counter-timer Physical Count register

CNTV_CTL c14 0 c3 1 32 Counter-timer Virtual Timer Control register

CNTV_CVAL - 3 c14 - 64 Counter-timer Virtual Timer CompareValue register

CNTV_TVAL c14 0 c3 0 32 Counter-timer Virtual Timer TimerValue register

CNTVCT - 1 c14 - 64 Counter-timer Virtual Count register

CP15ISB c7 0 c5 4 32 Instruction Synchronization Barrier System instruction

CP15DSB c7 0 c10 4 32 Data Synchronization Barrier System instruction

CP15DMB c7 0 c10 5 32 Data Memory Barrier System instruction

DLR c4 3 c5 1 32 Debug Link Register

DSPSR c4 3 c5 0 32 Debug Saved Program Status Register

TPIDRURO c13 0 c0 3 32 User Read Only Thread ID Register

TPIDRURW c13 0 c0 2 32 User Read/Write Thread ID Register

B1 AArch32 system registers

B1.1 AArch32 architectural system register summary

reserved.

B1-122

Non-Confidential

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ARM Cortex-A76 Core Specifications

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