ARM Cortex-A76 Core User Manual

D9.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
The TRCRSCTLRn controls the trace resources. There are eight resource pairs, the first pair is
predefined as {0,1,pair=0} and having reserved select registers. This leaves seven pairs to be
implemented as programmable selectors.
Bit field descriptions
The TRCRSCTLRn is a 32-bit register.
31 016 1520 19
INV
PAIRINV
22 21
SELECTGROUP
18 8 7
RES0
Figure D9-58 TRCRSCTLRn bit assignments
RES0, [31:22]
RES0 Reserved.
PAIRINV, [21]
Inverts the result of a combined pair of resources.
This bit is implemented only on the lower register for a pair of resource selectors.
INV, [20]
Inverts the selected resources:
0 Resource is not inverted.
1 Resource is inverted.
RES0, [19]
RES0 Reserved.
GROUP, [18:16]
Selects a group of resources. See the Arm
®
ETM Architecture Specification, ETMv4 for more
information.
RES0, [15:8]
RES0 Reserved.
SELECT, [7:0]
Selects one or more resources from the required group. One bit is provided for each resource
from the group.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCRSCTLRn can be accessed through the external debug interface, offset 0x208-0x023C.
D9 ETM registers
D9.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core