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B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1

The ID_ISAR6_EL1 provides information about the instruction sets that the core implements.

Bit field descriptions

ID_ISAR6_EL1 is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

31 8 7 0

4 3

RES0

Figure B2-55 ID_ISAR6_EL1 bit assignments

RES0, [31:8]

RES0 Reserved.

DP, [7:4]

UDOT and SDOT instructions. The value is:

0b0001 UDOT and SDOT instructions are implemented.

RES0, [3:0]

RES0 Reserved.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

ID_ISAR6_EL1 must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1,

ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1. See:

• B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 on page B2-233.

• B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 on page B2-235.

• B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 on page B2-237.

• B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1 on page B2-239.

• B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 on page B2-241.

• B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 on page B2-243.

Bit fields and details not provided in this description are architecturally defined. See the Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile.

B2 AArch64 system registers

B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1

reserved.

B2-245

Non-Confidential

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