D9.52 TRCPDCR, Power Down Control Register
The TRCPDCR request to the system power controller to keep the ETM trace unit powered up.
Bit field descriptions
The TRCPDCR is a 32-bit register.
31 4 3 2 0
PU
RES0
Figure D9-50 TRCPDCR bit assignments
RES0, [31:4]
RES0 Reserved.
PU, [3]
Powerup request, to request that power to the ETM trace unit and access to the trace registers is
maintained:
0 Power not requested.
1 Power requested.
This bit is reset to 0 on a trace unit reset.
RES0, [2:0]
RES0 Reserved.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCPDCR can be accessed through the external debug interface, offset 0x310.
D9 ETM registers
D9.52 TRCPDCR, Power Down Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-562
Non-Confidential
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