ARM Cortex-A76 Core User Manual

B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1
The ID_ISAR1_EL1 provides information about the instruction sets implemented by the core in
AArch32.
Bit field descriptions
ID_ISAR1_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Jazelle Interwork Immediate IfThen Extend Except_AR Except Endian
Figure B2-50 ID_ISAR1_EL1 bit assignments
Jazelle, [31:28]
Indicates the implemented Jazelle state instructions:
0x1 Adds the BXJ instruction, and the J bit in the PSR.
Interwork, [27:24]
Indicates the implemented Interworking instructions:
0x3 • The BX instruction, and the T bit in the PSR.
• The BLX instruction. The PC loads have BX-like behavior.
• Data-processing instructions in the A32 instruction set with the PC as the
destination and the S bit clear, have BX-like behavior.
Immediate, [23:20]
Indicates the implemented data-processing instructions with long immediates:
0x1 • The MOVT instruction.
• The MOV instruction encodings with zero-extended 16-bit immediates.
• The T32 ADD and SUB instruction encodings with zero-extended 12-bit immediates,
and other ADD, ADR, and SUB encodings cross-referenced by the pseudocode for
those encodings.
IfThen, [19:16]
Indicates the implemented If-Then instructions in the T32 instruction set:
0x1 The IT instructions, and the IT bits in the PSRs.
Extend, [15:12]
Indicates the implemented Extend instructions:
0x2 • The SXTB, SXTH, UXTB, and UXTH instructions.
• The SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH
instructions.
Except_AR, [11:8]
Indicates the implemented A profile exception-handling instructions:
0x1 The SRS and RFE instructions, and the A profile forms of the CPS instruction.
Except, [7:4]
Indicates the implemented exception-handling instructions in the A32 instruction set:
B2 AArch64 system registers
B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
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B2-235
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core