ARM Cortex-A76 Core User Manual

D3.14 EDRCR, External Debug Reserve Control Register
The EDRCR is part of the Debug registers functional group.
Bit field descriptions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
CSPA
CSE
RES0
Figure D3-12 EDRCR bit assignments
RES0, [31:4]
RES0 Reserved.
CSPA, [3]
Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The
actions on writing to this bit are:
0 No action.
1 Clear the EDSCR.PipeAdv bit to 0.
CSE, [2]
Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing
to this bit are:
0 No action
1 Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the core is in Debug state, the
EDSCR.ITO bit, to 0.
RES0, [1:0]
RES0 Reserved.
The EDRCR can be accessed through the internal memory-mapped interface and the external debug
interface, offset 0x090.
Usage constraints
This register is accessible as follows:
Off DLK OSLK SLK Default
Error Error Error WI WO
Configurations
EDRCR is in the Core power domain.
D3 Memory-mapped debug registers
D3.14 EDRCR, External Debug Reserve Control Register
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D3-432
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core