ARM Cortex-A76 Core User Manual

D9.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
The TRCVIIECTLR defines the address range comparators that control the ViewInst Include/Exclude
control.
Bit field descriptions
The TRCVIIECTLR is a 32-bit register.
31 0
EXCLUDE
16 15
INCLUDE
1920 34
RES0
Figure D9-70 TRCVIIECTLR bit assignments
RES0, [31:20]
RES0 Reserved.
EXCLUDE, [19:16]
Defines the address range comparators for ViewInst exclude control. One bit is provided for
each implemented Address Range Comparator.
RES0, [15:4]
RES0 Reserved.
INCLUDE, [3:0]
Defines the address range comparators for ViewInst include control.
Selecting no include comparators indicates that all instructions must be included. The exclude
control indicates which ranges must be excluded.
One bit is provided for each implemented Address Range Comparator.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCVIIECTLR can be accessed through the external debug interface, offset 0x084.
D9 ETM registers
D9.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
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D9-585
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core