ARM Cortex-A76 Core User Manual

C1.2 Debug register interfaces
The Debug architecture defines a set of debug registers.
The debug register interfaces provide access to these registers from:
• Software running on the core.
• An external debugger.
The Cortex-A76 core implements the Armv8 Debug architecture and debug events as described in the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile. It also implements
improvements to Debug introduced in Armv8.1 and Armv8.2.
C1.2.1 Core interfaces
System register access allows the core to directly access certain debug registers.
The external debug interface enables both external and self-hosted debug agents to access debug
registers. Access to the debug registers is partitioned as follows:
Debug registers
This function is system register based and memory-mapped. You can access the debug register
map using the APB slave port.
Performance monitor
This function is system register based and memory-mapped. You can access the performance
monitor registers using the APB slave port.
Activity monitor
This function is system register based and memory-mapped. You can access the activity monitor
registers using the APB slave port.
Trace registers
This function is memory-mapped.
ELA registers
This function is memory-mapped.
Related references
C1.4 External debug interface on page C1-370
C1.2.2 Breakpoints and watchpoints
The core supports six breakpoints, four watchpoints, and a standard Debug Communications Channel
(DCC).
A breakpoint consists of a breakpoint control register and a breakpoint value register. These two registers
are referred to as a Breakpoint Register Pair (BRP).
Four of the breakpoints (BRP 0-3) match only to virtual address and the other two (BRP 4 and 5) match
against either virtual address or context ID, or VMID. All the watchpoints can be linked to two
breakpoints (BRP 4 and 5) to enable a memory request to be trapped in a given process context.
C1.2.3 Effects of resets on debug registers
The core has the following reset signals that affect the debug registers:
nCPUPORESET
This signal initializes the core logic, including the debug, ETM trace unit, breakpoint,
watchpoint logic, and performance monitors logic. This maps to a Cold reset that covers reset of
the core logic and the integrated debug functionality.
nCORERESET
This signal resets some of the debug and performance monitor logic. This maps to a Warm reset
that covers reset of the core logic.
C1 Debug
C1.2 Debug register interfaces
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C1-367
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core