B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2
The VDISR_EL2 records that a virtual SError interrupt has been consumed by an ESB instruction
executed at Non-secure EL1.
Bit field descriptions
VDISR_EL2 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers
functional group.
Configurations
See B2.101.1 VDISR_EL2 at EL1 using AArch64 on page B2-286.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
This section contains the following subsection:
• B2.101.1 VDISR_EL2 at EL1 using AArch64 on page B2-286.
B2.101.1 VDISR_EL2 at EL1 using AArch64
VDISR_EL2 has a specific format when written at EL1.
The following figure shows the VDISR_EL2 bit assignments when written at EL1 using AArch64:
63
RES0
31
0
IDS
A ISS
30 2425 2332
Figure B2-84 VDISR_EL2 at EL1 using AArch64
RES0, [63:32]
RES0 Reserved.
A, [31]
Set to 1 when ESB defers an asynchronous SError interrupt.
RES0, [30:25]
RES0 Reserved.
IDS, [24]
Contains the value from VSESR_EL2.IDS.
ISS, [23:0]
Contains the value from VSESR_EL2, bits[23:0].
B2 AArch64 system registers
B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
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B2-286
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