D7.1 PMU snapshot register summary
The snapshot registers are visible in an implementation defined region of the PMU external debug
interface. Each time the debugger sends a snapshot request, information is collected to see how the code
is executed in the different cores.
The following table describes the PMU snapshot registers implemented in the core.
Table D7-1 PMU snapshot register summary
Offset Name Type Width Description
0x600
PMPCSSR_LO RO 32 D7.2 PMPCSSR, Snapshot Program Counter Sample Register on page D7-473
0x604
PMPCSSR_HI RO 32
0x608
PMPCIDSSR RO 32 D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register on page D7-474
0x60C
PMPCID2SSR RO 32 D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register on page D7-475
0x610
PMSSSR RO 32 D7.5 PMSSSR, PMU Snapshot Status Register on page D7-476
0x614
PMOVSSR RO 32 D7.6 PMOVSSR, PMU Overflow Status Snapshot Register on page D7-477
0x618
PMCCNTSR_LO RO 32 D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register on page D7-478
0x61C
PMCCNTSR_HI RO 32
0x620 + 4×n PMEVCNTSRn RO 32 D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5 on page D7-479
0x6F0
PMSSCR WO 32 D7.9 PMSSCR, PMU Snapshot Capture Register on page D7-480
D7 PMU snapshot registers
D7.1 PMU snapshot register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D7-472
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