ARM Cortex-A76 Core User Manual

About this book
This Technical Reference Manual is for the Cortex
®
-A76 core. It provides reference documentation and
contains programming details for registers. It also describes the memory system, the caches, the
interrupts, and the debug features.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rm Identifies the major revision of the product, for example, r1.
pn Identifies the minor revision or modification status of the product, for example, p2.
Intended audience
This manual is for system designers, system integrators, and programmers who are designing or
programming a System-on-Chip (SoC) that uses an Arm core.
Using this book
This book is organized into the following chapters:
Part A Functional description
This part describes the main functionality of the Cortex-A76 core.
Chapter A1 Introduction
This chapter provides an overview of the Cortex-A76 core and its features.
Chapter A2 Technical overview
This chapter describes the structure of the Cortex-A76 core.
Chapter A3 Clocks, resets, and input synchronization
This chapter describes the clocks, resets, and input synchronization of the Cortex-A76 core.
Chapter A4 Power management
This chapter describes the power domains and the power modes in the Cortex-A76 core.
Chapter A5 Memory Management Unit
This chapter describes the Memory Management Unit (MMU) of the Cortex-A76 core.
Chapter A6 Level 1 memory system
This chapter describes the L1 instruction cache and data cache that make up the L1 memory
system.
Chapter A7 Level 2 memory system
This chapter describes the L2 memory system.
Chapter A8 Reliability, Availability, and Serviceability (RAS)
This chapter describes the RAS features implemented in the Cortex-A76 core.
Chapter A9 Generic Interrupt Controller CPU interface
This chapter describes the Cortex-A76 core implementation of the Arm Generic Interrupt
Controller (GIC) CPU interface.
Chapter A10 Advanced SIMD and floating-point support
This chapter describes the Advanced SIMD and floating-point features and registers in the
Cortex-A76 core. The unit in charge of handling the Advanced SIMD and floating-point features
is also referred to as data engine in this manual.
Part B Register descriptions
This part describes the non-debug registers of the Cortex-A76 core.
Preface
Product revision status
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
16
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core