ARM Cortex-A76 Core User Manual

Chapter B1 AArch32 system registers
This chapter describes the system registers in the AArch32 state.
Chapter B2 AArch64 system registers
This chapter describes the system registers in the AArch64 state.
Chapter B3 Error system registers
This chapter describes the error registers accessed by the AArch64 error registers.
Chapter B4 GIC registers
This chapter describes the GIC registers.
Chapter B5 Advanced SIMD and floating-point registers
This chapter describes the Advanced SIMD and floating-point registers.
Part C Debug descriptions
This part describes the debug functionality of the Cortex-A76 core.
Chapter C1 Debug
This chapter describes the Cortex-A76 core debug registers and shows examples of how to use
them.
Chapter C2 Performance Monitor Unit
This chapter describes the Performance Monitor Unit (PMU) and the registers that it uses.
Chapter C3 Activity Monitor Unit
This chapter describes the Activity Monitor Unit (AMU).
Chapter C4 Embedded Trace Macrocell
This chapter describes the ETM for the Cortex-A76 core.
Part D Debug registers
This part describes the debug registers of the Cortex-A76 core.
Chapter D1 AArch32 debug registers
This chapter describes the debug registers in the AArch32 Execution state and shows examples of
how to use them.
Chapter D2 AArch64 debug registers
This chapter describes the debug registers in the AArch64 Execution state and shows examples of
how to use them.
Chapter D3 Memory-mapped debug registers
This chapter describes the memory-mapped debug registers and shows examples of how to use
them.
Chapter D4 AArch32 PMU registers
This chapter describes the AArch32 PMU registers and shows examples of how to use them.
Chapter D5 AArch64 PMU registers
This chapter describes the AArch64 PMU registers and shows examples of how to use them.
Chapter D6 Memory-mapped PMU registers
This chapter describes the memory-mapped PMU registers and shows examples of how to use
them.
Chapter D7 PMU snapshot registers
PMU snapshot registers are an IMPLEMENTATION DEFINED extension to an Armv8-A compliant PMU
to support an external core monitor that connects to a system profiler.
Chapter D8 AArch64 AMU registers
This chapter describes the AArch64 AMU registers and shows examples of how to use them.
Chapter D9 ETM registers
This chapter describes the ETM registers.
Preface
Using this book
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
17
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core