ARM Cortex-A76 Core User Manual

B2.91 SCTLR_EL2, System Control Register, EL2
The SCTLR_EL2 provides top-level control of the system, including its memory system at EL2.
Bit field descriptions
SCTLR_EL2 is a 32-bit register, and is part of:
• The Virtualization registers functional group.
• The Other system control registers functional group.
31 0
EE
2526 20 19 18 12 11 2 14 3
WXN
I C A M
SA
30 29 28 27 24 23 22 21 17 16 15 14 13 10 6 5
RES0
RES1
Figure B2-75 SCTLR_EL2 bit assignments
This register resets to 0x30C50838.
Configurations
If EL2 is not implemented, this register is RES0 from EL3.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.91 SCTLR_EL2, System Control Register, EL2
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B2-275
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core