ARM Cortex-A76 Core User Manual

D9.46 TRCITIDATAR, Integration Instruction ATB Data Register
The TRCITIDATAR sets the state of the ATDATAMn output pins shown in the TRCITIDATAR bit
assignments table.
Bit field descriptions
The TRCITIDATAR is a 32-bit register.
31 02 1
ATDATAM[31]
345
ATDATAM[23]
ATDATAM[15]
ATDATAM[7]
ATDATAM[0]
RES0
Figure D9-44 TRCITIDATAR bit assignments
RES0, [31:5]
RES0 Reserved.
ATDATAM[31], [4]
Drives the ATDATAM[31] output.
d
ATDATAM[23], [3]
Drives the ATDATAM[23] output.
d
ATDATAM[15], [2]
Drives the ATDATAM[15] output.
d
ATDATAM[7], [1]
Drives the ATDATAM[7] output.
d
ATDATAM[0], [0]
Drives the ATDATAM[0] output.
d
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCITIDATAR can be accessed through the external debug interface, offset 0xEEC.
d
When a bit is set to 0, the corresponding output pin is LOW. When a bit is set to 1, the corresponding output pin is HIGH. The TRCITIDATAR bit values correspond
to the physical state of the output pins.
D9 ETM registers
D9.46 TRCITIDATAR, Integration Instruction ATB Data Register
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D9-556
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core