B2.84 MIDR_EL1, Main ID Register, EL1
The MIDR_EL1 provides identification information for the core, including an implementer code for the
device and a device ID number.
Bit field descriptions
MIDR_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
VariantImplementer
31 23 20 19 16 15 4 3 0
Architecture PartNum Revision
24
Figure B2-68 MIDR_EL1 bit assignments
Implementer, [31:24]
Indicates the implementer code. This value is:
0x41 ASCII character 'A' - implementer is Arm Limited.
Variant, [23:20]
Indicates the variant number of the core. This is the major revision number x in the rx part of the
rxpy description of the product revision status. This value is:
0x3 r3p0.
Architecture, [19:16]
Indicates the architecture code. This value is:
0xF Defined by CPUID scheme.
PartNum, [15:4]
Indicates the primary part number. This value is:
0xD0B Cortex-A76 core.
Revision, [3:0]
Indicates the minor revision number of the core. This is the minor revision number y in the py
part of the rxpy description of the product revision status. This value is:
0x0 r3p0.
Configurations
The MIDR_EL1 is architecturally mapped to external MIDR_EL1 register.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.84 MIDR_EL1, Main ID Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-266
Non-Confidential
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