B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3
ICC_CTLR_EL3 controls aspects of the behavior of the GIC CPU interface and provides information
about the features implemented.
Bit field descriptions
ICC_CTLR_EL3 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The Security registers functional group.
• The GIC control registers functional group.
31
0
125678101113141516
CBPR_EL1S
CBPR_EL1NS
PMHE
PRIbitsIDbits
SEIS
A3V
RES0
341718
nDS
EOImode_EL3
EOImode_EL1S
EOImode_EL1NS
RM
Figure B4-4 ICC_CTLR_EL3 bit assignments
RES0, [31:18]
Reserved, RES0.
nDS, [17]
Disable Security not supported. Read-only and writes are ignored. The value is:
1 The CPU interface logic does not support disabling of security, and requires that
security is not disabled.
RES0, [16]
Reserved, RES0.
A3V, [15]
Affinity 3 Valid. This bit is RAO/WI.
SEIS, [14]
SEI Support. The value is:
0 The CPU interface logic does not support generation of SEIs.
IDbits, [13:11]
Identifier bits. The value is:
0x0 The number of physical interrupt identifier bits supported is 16 bits.
This field is an alias of ICC_CTLR_EL3.IDbits.
B4 GIC registers
B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-321
Non-Confidential
To Next Page
Loading...
