PRIbits, [10:8]
Priority bits. The value is:
0x4 The core supports 32 levels of physical priority with 5 priority bits.
Accesses to ICC_AP0R{1—3} and ICC_AP1R{1—3} are UNDEFINED.
RES0, [7]
Reserved, RES0.
PMHE, [6]
Priority Mask Hint Enable. The possible values are:
0 Disables use of ICC_PMR as a hint for interrupt distribution.
1 Enables use of ICC_PMR as a hint for interrupt distribution.
RM, [5]
Routing Modifier. This bit is RAZ/WI.
EOImode_EL1NS, [4]
EOI mode for interrupts handled at Non-secure EL1 and EL2.
Controls whether a write to an End of Interrupt register also deactivates the interrupt.
EOImode_EL1S, [3]
EOI mode for interrupts handled at Secure EL1.
Controls whether a write to an End of Interrupt register also deactivates the interrupt.
EOImode_EL3, [2]
EOI mode for interrupts handled at EL3.
Controls whether a write to an End of Interrupt register also deactivates the interrupt.
CBPR_EL1NS, [1]
Common Binary Point Register, EL1 Non-secure.
Control whether the same register is used for interrupt preemption of both Group 0 and Group 1
Non-secure interrupts at EL1 and EL2.
CBPR_EL1S, [0]
Common Binary Point Register, EL1 Secure.
Control whether the same register is used for interrupt preemption of both Group 0 and Group 1
Secure interrupt at EL1.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Generic Interrupt Controller Architecture Specification.
B4 GIC registers
B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-322
Non-Confidential
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