ARM Cortex-A76 Core User Manual

B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
ICC_SRE_EL1 controls whether the System register interface or the memory-mapped interface to the
GIC CPU interface is used for EL0 and EL1.
Bit field descriptions
ICC_SRE_EL1 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The GIC control registers functional group.
31
0
12
3
SRE
DFB
DIB
RES0
Figure B4-5 ICC_SRE_EL1 bit assignments
RES0, [31:3]
Reserved, RES0.
DIB, [2]
Disable IRQ bypass. The possible values are:
0x0 IRQ bypass enabled.
0x1 IRQ bypass disabled.
This bit is an alias of ICC_SRE_EL3.DIB
DFB, [1]
Disable FIQ bypass. The possible values are:
0x0 FIQ bypass enabled.
0x1 FIQ bypass disabled.
This bit is an alias of ICC_SRE_EL3.DFB
SRE, [0]
System Register Enable. The value is:
0x1 The System register interface for the current Security state is enabled.
This bit is RAO/WI. The core only supports a system register interface to the GIC CPU
interface.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Generic Interrupt Controller Architecture Specification.
B4 GIC registers
B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
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B4-323
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core