B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
ICC_SRE_EL1 controls whether the System register interface or the memory-mapped interface to the
GIC CPU interface is used for EL0 and EL1.
Bit field descriptions
ICC_SRE_EL1 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The GIC control registers functional group.
31
0
12
3
SRE
DFB
DIB
RES0
Figure B4-5 ICC_SRE_EL1 bit assignments
RES0, [31:3]
Reserved, RES0.
DIB, [2]
Disable IRQ bypass. The possible values are:
0x0 IRQ bypass enabled.
0x1 IRQ bypass disabled.
This bit is an alias of ICC_SRE_EL3.DIB
DFB, [1]
Disable FIQ bypass. The possible values are:
0x0 FIQ bypass enabled.
0x1 FIQ bypass disabled.
This bit is an alias of ICC_SRE_EL3.DFB
SRE, [0]
System Register Enable. The value is:
0x1 The System register interface for the current Security state is enabled.
This bit is RAO/WI. The core only supports a system register interface to the GIC CPU
interface.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Generic Interrupt Controller Architecture Specification.
B4 GIC registers
B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-323
Non-Confidential
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