ARM Cortex-A76 Core User Manual

B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
The ACTLR_EL3 provides IMPLEMENTATION DEFINED configuration and control options for EL3.
Bit field descriptions
ACTLR_EL3 is a 64-bit register, and is part of:
• The Other system control registers functional group.
• The Security registers functional group.
• The IMPLEMENTATION DEFINED functional group.
63 7 6 5 1 04 2
SMEN
PWREN
ECTLREN
ACTLREN
810111213
ERXPFGEN
RES0
CLUSTERPMUEN
3
AMEN
Figure B2-3 ACTLR_EL3 bit assignments
RES0, [63:13]
RES0 Reserved.
CLUSTERPMUEN, [12]
Performance Management Registers enable. The possible values are:
0 CLUSTERPM* registers are not write-accessible from a lower Exception level. This is
the reset value.
1 CLUSTERPM* registers are write-accessible from EL2 and EL1 Secure.
SMEN, [11]
Scheme Management Registers enable. The possible values are:
0 Registers CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR,
CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are not write-accessible from
EL2 and EL1 Secure. This is the reset value.
1 Registers CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR,
CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are write-accessible from
EL2 and EL1 Secure.
TSIDEN, [10]
Thread Scheme ID Register enable. The possible values are:
0 Register CLUSTERTHREADSID is not write-accessible from EL2 and EL1 Secure.
This is the reset value.
1 Register CLUSTERTHREADSID is write-accessible from EL2 and EL1 Secure.
RES0, [9:8]
B2 AArch64 system registers
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-147
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core