B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
The ACTLR_EL3 provides IMPLEMENTATION DEFINED configuration and control options for EL3.
Bit field descriptions
ACTLR_EL3 is a 64-bit register, and is part of:
• The Other system control registers functional group.
• The Security registers functional group.
• The IMPLEMENTATION DEFINED functional group.
63 7 6 5 1 04 2
SMEN
PWREN
ECTLREN
ACTLREN
810111213
ERXPFGEN
RES0
CLUSTERPMUEN
3
AMEN
Figure B2-3 ACTLR_EL3 bit assignments
RES0, [63:13]
RES0 Reserved.
CLUSTERPMUEN, [12]
Performance Management Registers enable. The possible values are:
0 CLUSTERPM* registers are not write-accessible from a lower Exception level. This is
the reset value.
1 CLUSTERPM* registers are write-accessible from EL2 and EL1 Secure.
SMEN, [11]
Scheme Management Registers enable. The possible values are:
0 Registers CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR,
CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are not write-accessible from
EL2 and EL1 Secure. This is the reset value.
1 Registers CLUSTERACPSID, CLUSTERSTASHSID, CLUSTERPARTCR,
CLUSTERBUSQOS, and CLUSTERTHREADSIDOVR are write-accessible from
EL2 and EL1 Secure.
TSIDEN, [10]
Thread Scheme ID Register enable. The possible values are:
0 Register CLUSTERTHREADSID is not write-accessible from EL2 and EL1 Secure.
This is the reset value.
1 Register CLUSTERTHREADSID is write-accessible from EL2 and EL1 Secure.
RES0, [9:8]
B2 AArch64 system registers
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-147
Non-Confidential
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