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0 Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN,

CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are not write-

accessible from EL1 Non-secure. This is the reset value.

1 Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN,

CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are write-accessible

from EL1 Non-secure if they are write-accessible from EL2.

RES0, [6]

RES0 Reserved.

ERXPFGEN, [5]

Error Record Registers enable. The possible values are:

0 ERXPFG* are not write-accessible from EL1 Non-secure. This is the reset value.

1 ERXPFG* are write-accessible from EL1 Non-secure if they are write-accessible from

EL2.

AMEN, [4]

Activity Monitor enable. The possible values are:

0 Non-secure accesses from EL1 and EL0 to activity monitor registers are trapped to

EL2.

1 Non-secure accesses from EL1 and EL0 to activity monitor registers are not trapped to

EL2.

RES0, [3:2]

RES0 Reserved.

ECTLREN, [1]

Extended Control Registers enable. The possible values are:

0 CPUECTLR and CLUSTERECTLR are not write-accessible from EL1 Non-secure.

This is the reset value.

1 CPUECTLR and CLUSTERECTLR are write-accessible from EL1 Non-secure if they

are write-accessible from EL2.

Configurations

Bit fields and details that are not provided in this description are architecturally defined. See the

Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile.

B2 AArch64 system registers

B2.6 ACTLR_EL2, Auxiliary Control Register, EL2

reserved.

B2-146

Non-Confidential

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