ARM Cortex-A76 Core User Manual

D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0
The AMUSERENR_EL0 enables or disables EL0 access to the activity monitors.
Bit field descriptions
The AMUSERENR_EL0 is a 32-bit register.
31 0
1
RES0
EN
Figure D8-2 MUSERENR_EL0 bit assignments
RES0, [31:1]
Reserved, RES0.
EN, [0]
Traps EL0 accesses to the activity monitor registers to EL1. The possible values are:
0 EL0 accesses to the activity monitor registers are trapped to EL1.
1 EL0 accesses to the activity monitor registers are not trapped to EL1. Software can
access all activity monitor registers at EL0.
Configurations
There are no configuration notes.
Usage constraints
Accessing the AMUSERENR_EL0
To access the AMUSERENR_EL0:
MRS <Xt>, AMUSERENR_EL0 ; Read AMUSERENR_EL0 into Xt
MSR AMUSERENR_EL0, <Xt> ; Write Xt to AMUSERENR_EL0
Register access is encoded as follows:
Table D8-5 AMUSERENR_EL0 encoding
op0 op1 CRn CRm op2
11 011 1111 1010 111
This register is accessible as follows:
EL0 EL1 EL2 EL3
RO RW RW RW
Note
AMUSERENR_EL0 is always RO at EL0 and not trapped by the EN bit.
D8 AArch64 AMU registers
D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0
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D8-487
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core