ARM Cortex-A76 Core

Traps and enables
If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are
trapped to EL2.
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped
to EL3.
If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1.
D8 AArch64 AMU registers
D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0
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D8-486
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