ARM Cortex-A76 Core User Manual

D9.31 TRCIDR2, ID Register 2
The TRCIDR2 returns the maximum size of six parameters in the trace unit.
The parameters are:
• Cycle counter.
• Data value.
• Data address.
• VMID.
• Context ID.
• Instruction address.
Bit field descriptions
The TRCIDR2 is a 32-bit register.
31 025 24 1415 10 9 5 4
IASIZE
29 28 20 19
CIDSIZEVMIDSIZEDASIZEDVSIZECCSIZE
RES0
VMIDOPT
Figure D9-29 TRCIDR2 bit assignments
RES0, [31]
RES0 Reserved.
VMIDOPT, [30:29]
Indicates the options for observing the Virtual context identifier:
0x1 VMIDOPT is implemented.
CCSIZE, [28:25]
Size of the cycle counter in bits minus 12:
0x0 The cycle counter is 12 bits in length.
DVSIZE, [24:20]
Data value size in bytes:
0x00 Data value tracing is not implemented.
DASIZE, [19:15]
Data address size in bytes:
0x00 Data address tracing is not implemented.
VMIDSIZE, [14:10]
Virtual Machine ID size:
0x4 Maximum of 32-bit Virtual Machine ID size.
CIDSIZE, [9:5]
Context ID size in bytes:
D9 ETM registers
D9.31 TRCIDR2, ID Register 2
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D9-537
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core