ARM Cortex-A76 Core User Manual

C2.1 About the PMU
The Cortex-A76 core includes performance monitors that enable you to gather various statistics on the
operation of the core and its memory system during runtime. These provide useful information about the
behavior of the core that you can use when debugging or profiling code.
The PMU provides six counters. Each counter can count any of the events available in the core. The
absolute counts recorded might vary because of pipeline effects. This has negligible effect except in
cases where the counters are enabled for a very short time.
Related references
C2.3 PMU events on page C2-374
C2 Performance Monitor Unit
C2.1 About the PMU
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C2-372
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core