B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register
The ERR0PFGFR is the Cortex-A76 node register that defines which fault generation features are
implemented.
Bit field descriptions
ERR0PFGFR is a 32-bit register and is RO.
31
0
RES0
130 29 234567
R
PFG
CE
DE
UEO
UER
UEU
UC
Figure B3-7 ERR0PFGFR bit assignments
PFG, [31]
Pseudo Fault Generation. The value is:
1 The node implements a fault injection mechanism.
R, [30]
Restartable bit. When it reaches zero, the Error Generation Counter restarts from the
ERR0PFGCDN value or stops. The value is:
1 This feature is controllable.
[29:7]
RES0 Reserved.
CE, [6]
Corrected Error generation. The value is:
1 This feature is controllable.
DE, [5]
Deferred Error generation. The value is:
1 This feature is controllable.
UEO, [4]
Latent or Restartable Error generation. The value is:
0 The node does not support this feature.
UER, [3]
Signaled or Recoverable Error generation. The value is:
0 The node does not support this feature.
UEU, [2]
Unrecoverable Error generation. The value is:
0 The node does not support this feature.
B3 Error system registers
B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register
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reserved.
B3-305
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