ARM Cortex-A76 Core User Manual

D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
The TRCSEQEVRn defines the sequencer transitions that progress to the next state or backwards to the
previous state. The ETM trace unit implements a sequencer state machine with up to four states.
Bit field descriptions
The TRCSEQEVRn is a 32-bit register.
31 016
B SEL
F SEL
15 8 7111214 4 36
B TYPE F TYPE
RES0
Figure D9-59 TRCSEQEVRn bit assignments
RES0, [31:16]
RES0 Reserved.
B TYPE, [15]
Selects the resource type to move backwards to this state from the next state:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [14:12]
RES0 Reserved.
B SEL, [11:8]
Selects the resource number, based on the value of B TYPE:
When B TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When B TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
F TYPE, [7]
Selects the resource type to move forwards from this state to the next state:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [6:4]
RES0 Reserved.
F SEL, [3:0]
Selects the resource number, based on the value of F TYPE:
When F TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When F TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSEQEVRn registers can be accessed through the external debug interface, offsets:
D9 ETM registers
D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core